Multi-SERDES PHY SATA3/PCIe2/XAUI/Fiber Channel

The Innosilicon Multi-SERDES PHY is a highly configurable design that supports SATA3, PCIe2 and XAUI with full compliance. High data rates are accurately achieved through fully programmable TX drivers and auto-calibrated on-die terminations.

The design is completely self-contained including: I/O pads, primary and secondary ESD for simple integration and production testing is simplified through at-speed BIST, loopback and boundary scan.

As with all Innosilicon IP, we are ready to provide the custom solution that meets your needs.

KEY FEATURES:

Silicon proven in 14, 28, 40, 55 and 65nm across SMIC, TSMC and Global Foundries
Compliant with SATA3(6Gb/s), PCIe4.0(16Gb/s), USB3.1(10Gb/s) and XAUI(3.125Gb/s)
TX drivers are programmable for amplitude, slew rate and de-emphasis to ensure a 200mV to 800mV signal window as appropriate.
On-die terminations are auto-calibrated during handshake for both value and matching
Incorporates spread spectrum clocking (SSC) for all interface implementations with control for spectrum offset, range shape and skew rate
Embedded primary & secondary ESD protection
Integrated IO pads
Production test support is optimized through high coverage at-speed BIST, loopback and boundary scan support

INNOSILICON ADVANTAGES:

Low power consumption
Fully customizable
Small area
Simple integration process
Available options include

lTest chips and test boards
lFPGA integration support
lChip level integration support

BLOCK DIAGRAM:

EXAMPLE APPLICATIONS:

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Serdes Q&A

What package can you choose?

Supports small form-factor LQFP/LQFN; Supports BGA

What makes our Serdes different?

Supports multi-protocol combo design of SATA/PCIe/U3/XAUI/FC
Supports multi-channel design, sharing common module to reduce die size and package pin number
Compatible with various types of package, such as LQFP/LQFN, WB/FC, and BGA